A conventional semiconductor arrangement, e.g. an arrangement including a plurality of power semiconductor devices, e.g. a press pack array, may be formed by at least partially encapsulating the plurality of power semiconductor devices and a electrically conductive plate, which may form a common terminal, e.g. a common controlled terminal, e.g. a common collector contact, in an, e.g. dielectric, encapsulation material. The encapsulation may be arranged to enclose the electrically conductive plate from five sides, i.e. on a top surface on which the power semiconductor devices may be arranged, and on side surfaces contacting the top surface. A bottom surface of the electrically conductive plate may be free or at least partially free from the encapsulation material.
This means that an interface between the electrically conductive plate and the encapsulation material may be created that may be open to an outside environment. Through this interface, humidity or other substances that may be harmful to the semiconductor arrangement may enter the semiconductor arrangement and reach the power semiconductor devices, thereby potentially damaging the semiconductor arrangement.
Furthermore, the semiconductor arrangement may for its operation be held in a holding device. In a case where the holding device attaches to the sides of the semiconductor arrangement, it may have to attach to the encapsulation material, which may represent a weak spot of the semiconductor arrangement.